This invention relates to data communication systems, and more particularly, to a system for providing interleaved access to a lookup address table in a multiport network switching system.
A multiport switch may be provided in a data communication network to enable data communication between multiple network nodes connected to various ports of the switch. A logical connection may be created between receive ports and transmit ports of the switch to forward received frames to appropriate destinations. Based on frame header information, a decision making engine selectively controls forwarding received frames to a destination station. The decision making engine comprises various units performing decision making operations. Some of the engine units need to access a lookup table that stores such data as source and destination address information and ports identification (ID) data. A multiple-port memory can be used to enable the engine units to access the address table via separate ports. However, such a memory occupies a substantial area on the chip and requires extremely high memory access rate to maintain high-speed operations.
To speed up the decision making process without using a multiple-port address table memory, it would be desirable to provide various units of the decision making engine with interleaved access to the lookup table.
The invention offers a novel method of providing interleaved access to an address lookup table in a multiport communication system having a decision making engine that controls data switching between receive and transmit ports. Data blocks representing received data packets are processed by first and second logic circuits of the decision making engine in accordance with a prescribed algorithm. The first and second logic circuits are enabled to alternately access the address table.
For example, the first logic circuit may access the address table for searching source address information, and the second logic circuit may access the address table for searching destination address information. The first and second logic circuits may be connected in a pipeline.
In accordance with one aspect of the invention, the decision making engine includes an address table storage for storing an address table having address information relating to the plurality of ports, and an interleaved address table access circuit for enabling the first and second logic circuits to alternately access the address table storage. The address table storage has a single port for providing both the first and second logic circuits with access to the address table.
Preferably, the interleaved address table access circuit comprises an arbitration circuit that provides the first and second logic circuits with access to the address table in alternate time slots allocated to these logic circuits. The arbitration circuit may enable the first and second logic circuits to automatically access the address table without requests for access from these logic circuits.
Also, the arbitration circuit may enable a third logic circuit of the decision making engine to access the address table in a pre-selected time slot allocated to the third logic circuit. For example, the third logic circuit may be an aging circuit that checks a pre-selected bit combination in the address table to delete an entry from the address table if the bit combination is in a predetermined state.
The third logic circuit may supply the arbitration circuit with a request signal to request access to the address table. If no request signal from the third logic circuit is received, the arbitration circuit may enable the first or the second logic circuit to access the address table in the time slot allocated to the third logic circuit.
Further, the arbitration circuit may provide a host processor with access to the address table in a pre-selected time slot allocated to the host processor.
The host processor access may be enabled in response to a request signal from the host processor. However, if no request signal from the host processor is received, the arbitration circuit enables the first or the second logic circuit to access the address table in the time slot allocated to the host processor.
Various objects and features of the present invention will become more readily apparent to those skilled in the art from the following description of a specific embodiment thereof, especially when taken in conjunction with the accompanying drawings.